1. Field of the Invention
The present invention generally relates to power conversion circuits, and the preferred embodiments provide improved power conversion circuits for e.g., uninterruptible power supplies.
2. Background Discussion
Uninterruptible power supplies (UPSs) are commonly used to provide power to critical equipment that must not experience even short duration brownouts or blackouts. For example, computer servers, computer networks, telecommunications electronics and medical devices are often powered by an uninterruptible power supply.
A UPS device typically has an AC-DC-AC converter and backup battery that is activated in case the alternating current (AC) line power is temporarily disconnected or falls below a voltage threshold.
FIG. 5 shows one illustrative and non-limiting conventional UPS circuit according to the background art. The illustrated conventional UPS circuit includes an input rectifier (having switches Q1, Q2) and an output inverter (having switches Q3, Q4) connected in series. The input rectifier converts AC input power to DC power, and the output inverter converts the DC power to AC output power. Typically, the switches Q1, Q2, Q3, and Q4 will be MOSFET devices or insulated gate bipolar transistors (IGBTs). The switches Q1, Q2 Q3, and Q4 are controlled by a gate drive circuit (not shown). Storage capacitors C1 C2 store DC power. Typically, an isolation transformer T is provided. The input rectifier switches Q1, Q2 receive AC line power and provide direct current (DC) power to the inverter switches Q3, Q4. The inverter switches Q3, Q4 are typically operated according to a pulse-width modulation (PWM) scheme. The PWM waveform is filtered by output inductor Lo and output capacitor Co to create a smooth AC output waveform. With this illustrative arrangement, the voltage and frequency of the AC output can be accurately controlled independently of the AC input.
A variety of topologies are known for providing a controlled DC power source. One such topology is a full-bridge current-fed design. In such a design, a DC current source is alternately switched between diagonals of a full-bridge switching network on a primary side of a transformer. By controlling the periods during which each diagonal is conducting, a desired output voltage on the secondary side of the transformer can be obtained. However, limiting stresses on semiconductor switching components of the bridge is an inherent challenge in such a topology. Toward that end, a variety of snubber, clamp and other stress-reducing circuit designs have been proposed. In addition to controlling the conduction and non-conduction of the bridge circuit, the stress-reducing circuits typically require some control mechanism. One example of a full bridge power converter with an active clamp circuit is described in U.S. Pat. No. 6,038,142. In the described system, an active clamp circuit composed of a capacitor and a switching MOSFET is connected across the DC side of a full-bridge network of switching transistors. The voltage across the switching network is monitored during the switching cycle. When that voltage reaches zero (called a “zero voltage transition” in the '142 patent), the non-conducting switches in the bridge are turned on.
A number of other background references are seen in the following U.S. Patents, the entire disclosures of which are each incorporated herein by reference: 1) U.S. Pat. No. 6,898,093, entitled Power Conversion Circuit With Clamp and Soft Start (hereinafter the '093 patent); and 2) U.S. Pat. No. 4,646,222 entitled Inverter Provided With An Overvoltage Clamping Circuit (hereinafter the '222 patent). The '222 patent indicates, among other things, that “[c]onventionally, when an output voltage of a voltage source inverter is boosted by a transformer, a resonance voltage on the order of tens of kilohertz is caused due to the leakage inductance of the transformer and the leakage capacitances of a load cable and a load AC motor.” With reference to the '093 patent, the patent teaches a power converter that includes:                [A] current source providing an input current, a transformer having primary and secondary windings, a switch network coupling the current source and the primary winding, and a clamping circuit coupled to the switch network. An output bus is coupled to the secondary winding and provides an output voltage. A control circuit has inputs based on the output voltage and the input current, and generates switch network control signals based on those inputs. The control circuit also generates clamping circuit control signals based on the switch network control signals. The power converter may also include a start-up control circuit configured to selectively control the switch network and the clamping circuit so as to raise the output voltage to a desired level. In some embodiments, the switch network is a full bridge, and the clamping circuit includes first and second clamping switches.        See Abstract.        According to the '093 patent:        The present invention address many of the challenges presented by the above described and other prior designs. Instead of requiring a separate monitoring circuit to check for a zero voltage transition point in the switching network, a circuit according to the present invention controls operation of both switching and clamping transistors based on output bus voltage during normal operation. During a start-up mode of operation, a microprocessor can be used to control the switching and clamping transistors according to a preset cycle until the output voltage reaches a desired starting level.        In one illustrative embodiment, a power converter includes a current source providing an input current, a transformer having primary and secondary windings, a switch network coupling the current source and the primary winding, and a clamping circuit coupled to the switch network. An output bus is coupled to the secondary winding and provides an output voltage. A control circuit has inputs based on the output voltage and the input current, and generates switch network control signals based on those inputs. The control circuit also generates clamping circuit control signals based on the switch network control signals. The power converter may also include a start-up control circuit configured to selectively control the switch network and the clamping circuit so as to raise the output voltage to a desired level. In some illustrative embodiments, the switch network is a full bridge, and the clamping circuit includes first and second clamping switches.        See Summary of the Invention.        
More particularly, FIGS. 6 and 7 depict a system as set forth in the '093 patent. In this regard, FIG. 6 is a schematic diagram of a power conversion circuit 10 according to an illustrative embodiment of the invention. Power conversion circuit 10 includes a transformer 12. In one embodiment, transformer 12 has a 1:1 winding ratio, but may have other winding ratios in other configurations. The primary side of transformer 12 is shown to the left in FIG. 1. Voltage source 14 may be a rectified DC input (e.g., rectified AC line input), DC input supplied by a battery, or other DC input. Coupled to voltage source 14 is a boost inductor 16. A Hall effect transducer 18 or other appropriate current sensor is interposed between voltage source 14 and inductor 16, and provides an output signal E (the purpose of which is described below). Voltage source 14 and inductor 16 are coupled to the primary winding of transformer 12 by switch transistors 20, 22, 24 and 26. Switch transistors 20, 22, 24 and 26 form a full bridge switch network. Switch transistors 20, 22, 24 and 26 are controlled by signals A(1), B(1), B(2) and A(2) applied to their respective gates. When signals A(1) and A(2) are high and signals B(1) and B(2) are low, current flows through the “A” diagonal of the bridge by passing through high side transistor 20, through the primary winding of transformer 12, and then through low side transistor 26. When signals A(1) and A(2) are low and signals B(1) and B(2) are high, current flows through the “B” diagonal of the bridge by passing through high side transistor 22, through the primary winding of transformer 12 (now in the opposite direction), and then through low side transistor 24. When signals A(1), A(2), B(1) and B(2) are all high, conversion circuit 12 is in a shorted primary condition, and current flows to ground from the output of boost inductor 16 through switch transistors 20, 22, 24 and 26, bypassing the primary winding of transformer 12.
Clamping switch transistors 28 and 30, together with clamping capacitor 32, are located on the AC side of the bridge. In other words, the source of clamping switch transistor 28 is coupled to the junction between the source of transistor 20 and the primary winding of transformer 12, and the source of clamping switch transistor 30 is coupled to the junction between the source of transistor 22 and the primary winding of transformer 12. Also shown as part of transistors 28 and 30 are body diodes which allow current to flow from the sources to the drains of transistors 28 and 30. Body diodes may (and typically would) also be present in transistors 20, 22, 24 and 26, but are omitted so as not to obscure the drawing. Clamping switch transistor 28 is controlled by signal C applied to its gate. Clamping switch transistor 30 is controlled by signal D applied to its gate. When signals A(1), A(2) and C are high and signals B(1), B(2) and D are low, clamping switch transistor 28 and clamping capacitor 32 connect the primary side of transformer 12 to ground. When signals A(1), A(2) and C are low and signals B(1), B(2) and D are high, clamping switch transistor 30 and clamping capacitor 32 connect the primary side of transformer 12 to ground.
On the secondary side of the transformer, an output voltage VOUT is provided across an output bus formed by terminals 35 and 37. Diodes 38, 40, 42 and 44 form a rectifying bridge coupling the secondary winding of transformer 12 to the output bus. Capacitors 34 and 36 form a voltage doubler. A signal F, the purpose of which is described below, is tapped from the output bus.
FIG. 7 is a schematic diagram of the control circuitry 100 for power conversion circuit 10 during normal operating mode. As used herein, “normal operating mode” refers to a state in which power conversion circuit 10 is being used to provide a desired voltage output. Conversely, “start-up mode” refers to a state in which power conversion circuit 10 is being initially activated (e.g., from a condition in which the entire system is turned off or otherwise substantially powered down), and in which various circuit components are being readied for normal operating mode. One input to control circuitry 100 is the signal F, a feedback signal from the output bus (FIG. 6). Output voltage feedback signal F and a reference voltage VREF are provided to a Proportional Integrator Differentiator (PID) 110 formed by operational amplifier (op amp) 112, resistors 114 and 116, and capacitors 118 and 120. The output signal of PID 110, labeled V1-REF, is provided through resistor 122 to the inverting node of op amp 124. Also provided to the inverting node of op amp 124, through resistor 126, is the signal E generated from Hall effect transformer 18 (FIG. 6) measuring current between voltage source 14 and boost inductor 16. A feedback loop having resistor 128 and capacitor 130 connects the output node and inverting node of op amp 124. The output signal V1-x from op amp 124 is then fed to the non-inverting input of comparator 132. The inverting input of comparator 132 receives the saw tooth waveform signal SAW from carrier generator 134. The output of comparator 132, labeled SHORT, is fed to one input of OR gate 136 and to one input of OR gate 138.
Carrier generator 134 also provides a clocking signal CLOCK to flip flop 140. The clocking signal has the same frequency as the SAW signal. Flip flop 140 then outputs two signals, labeled PHASE_A and PHASE_B, that are respectively provided as inputs to OR gates 136 and 138 via RC networks 152, 154 and 156, 158. The SHORT signal is provided as a second input to OR gates 136 and 138. The output of OR gate 136 then provides the control signals B(1) and B(2) to the gates of switch transistors 22 and 24. The output of OR gate 138 provides the control signals A(1) and A(2) to the gates of switch transistors 20 and 26. Control signal C for clamping switch transistor 28 is provided by AND gate 142, the inputs to which are the inverted output of OR gate 136 (via inverter 141) and the non-inverted output of OR gate 138. Control signal D for clamping switch transistor 30 is provided by AND gate 144, the inputs to which are the inverted output of OR gate 138 (via inverter 143) and the non-inverted output of OR gate 136.
While a number of systems and methods are known in the art, there remains a need in the art for improved systems and methods that improve upon the above and/or other known technologies.